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-rw-r--r--arch/x86_64/hal/paging.c17
-rw-r--r--arch/x86_64/hal/paging.h4
2 files changed, 13 insertions, 8 deletions
diff --git a/arch/x86_64/hal/paging.c b/arch/x86_64/hal/paging.c
index 47c79f3..8eee066 100644
--- a/arch/x86_64/hal/paging.c
+++ b/arch/x86_64/hal/paging.c
@@ -39,7 +39,7 @@ paging_get_pml4(void)
void
paging_pml4_switch(uintptr_t pml4)
{
- __asm__ volatile("movq %0, %%cr3":: "r"(pml4));
+ __asm__ volatile("movq %0, %%cr3":: "r"(pml4): "memory");
}
static struct int_stackframe*
@@ -60,11 +60,13 @@ s_int_handle_pf_early(struct int_stackframe *frame)
uint64_t value;
} pf_error = { .value = frame->int_err };
- kprintf("Kernel has encountered a page fault exception early in initializaiton\n");
+ kprintf("Kernel has encountered a page fault"
+ "exception early in initializaiton\n");
kprintf("%s %s during %s\n",
pf_error.wr ? "Wrote to" : "Read from",
pf_error.p ? "Present" : "Non-present",
pf_error.id ? "Instruction fetch" : "Data access");
+
uintptr_t cr2 = 0;
__asm__ volatile("movq %%cr2, %0": "=r"(cr2));
kprintf("Faulting address: %p\n", cr2);
@@ -91,7 +93,8 @@ s_pagedir_get_pml1(page_t *pml4, uintptr_t vptr)
return 0;
}
- page_t *pml2 = (page_t*)(((uintptr_t)pml3[pml3i].paddr << 12) | IDENT_VIRT_BASE);
+ page_t *pml2 = (page_t*)(((uintptr_t)pml3[pml3i].paddr << 12)
+ | IDENT_VIRT_BASE);
size_t pml2i = PML2I(vptr);
if(!pml2[pml2i].p) {
errno = ENOMAP;
@@ -167,14 +170,16 @@ int pagedir_map_table(page_t *pml4,
goto map_table;
}
- page_t *pml3 = (page_t*)(((uintptr_t)pml4[pml4i].paddr << 12) | IDENT_VIRT_BASE);
+ page_t *pml3 = (page_t*)(((uintptr_t)pml4[pml4i].paddr << 12)
+ | IDENT_VIRT_BASE);
size_t pml3i = PML3I(vptr);
if(!pml3[pml3i].p) {
target_table = &pml3[pml3i];
goto map_table;
}
- page_t *pml2 = (page_t*)(((uintptr_t)pml3[pml3i].paddr << 12) | IDENT_VIRT_BASE);
+ page_t *pml2 = (page_t*)(((uintptr_t)pml3[pml3i].paddr << 12)
+ | IDENT_VIRT_BASE);
size_t pml2i = PML2I(vptr);
if(!pml2[pml2i].p) {
target_table = &pml2[pml2i];
@@ -327,7 +332,7 @@ paging_pml4_init(void)
/*Identity pages are mapped as huge pages starting at the 256'th PML3 entry.
*We want to support any range of physical memory up to several TiB, so
*the mapper has to consider multiple heirarchies of huge pages.*/
-
+
for(size_t l3 = 0; l3 < IDENT_MASSIVEPAGES; l3++) {
uintptr_t ident_pml3_pptr = KPTR_TOPHYS(&ident_pml3[l3]);
diff --git a/arch/x86_64/hal/paging.h b/arch/x86_64/hal/paging.h
index 3e16003..5b7260c 100644
--- a/arch/x86_64/hal/paging.h
+++ b/arch/x86_64/hal/paging.h
@@ -35,8 +35,8 @@ typedef union page_table_entry
#define PAGE_ACCESSED 0b100000
#define PAGE_DIRTY 0b1000000
#define PAGE_PS 0b10000000
-#define PAGE_GLOBAL 0b100000000
-#define PAGE_XD (1ULL << 63)
+#define PAGE_GLOBAL 0b000000000
+#define PAGE_XD (0ULL << 63)
extern void *_kernel_physptr;